• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The invention relates to radio engineering. The purpose of the invention is to increase speed. For implementing the method of processing digital signals, a device is used comprising a converter of the ternary signal into a signal of a module and a sign, a delay line 2 having two branches with
    公开号:SU1655309A3
    申请号:SU843818872
    申请日:1984-11-30
    公开日:1991-06-07
    发明作者:Шенк Хайнрих
    申请人:Сименс Аг (Фирма)；
    IPC主号:
    专利说明:

    The invention relates to radio engineering and can be used in signal transmission networks for adaptive distortion correction.
    The purpose of the invention is to increase speed.
    The drawing shows an example of the implementation of a device for implementing a method of processing digital signals of the type of preferably adaptive transversal filter.
    The device contains a converter of 1 ternary signal into a signal of a module and a sign, a delay line 2 having two branches 2.1 and 2.2 and taps 2.1.0-2.1. (N-1) and 2.2.0-2.2. (N-1), multichannel polling switch 3 containing multiplexers 3.1.1-3.1.W 3.2.1-3.2.W, encoding unit 4, accumulator 5 partial sums, unit 6 summation containing adder 6.1 and input registers 6.2 and 6.3, additional unit 7 summation, containing adder 7.1 and input registers 7.2 - and 7.3, counter 8, multiplier 9, switch Yu, input 11.
    In the proposed method of processing digital signals according to the type of preferably adaptive transversal filter, the following processing algorithm is used.
    In a (N-1) -stitch transversal filter, the magnitude of the output element tk contained in the time element k can be described as
    NIH .j C ;,
    where .- - the value of the elements of the signal
    the laterals appearing in this temporary element in the individual laterals of the delay line 2; C - N filter coefficients,
    which define the properties of the filter (frequency response, time response). In the case of adaptive filter settings, individual coefficients C; The filter can be gradually set by iteration, which can be described using the formula
    c.Wi c: (Krs uGX .;
    where and is the so-called adjustment value, which determines the installation time of the filter in the desired state and the required coefficients of the word length and thus the accuracy of the filter, which, however, also cannot be selected too large to ensure a reliable installation (convergence of the filter), D (5 is the error remaining in relation to the pursued given value of the considered element of the output signal. Instead of such an error, you can, if necessary, use only its zyp sign (D.c) as the installation error Theurillat.
    The proposed device has first of all at its entrance supplied
    taps (0,1,2,3N-, N-1) (11-1) step speed line 2 delay, the input of which receives the digital signal to be processed. In the source 1, the input termination signal 2 to the input 11 of the delay line 2 to be processed is first recoded into a pair of binary signals covering the binary signal of the module and; voich51655);) 9
    sign signal. Line 2 delay
    It has a CN-1) -step 2.1 branch, which receives a binary sign signal, and (N-1) -step 2.2. which receives the binary signal module. Each group of W, one after another, of follow-up taps of a delay line 2, having N / W tap groups, is connected to a group of inputs corresponding to this tap group, of a multi-channel switch 3, having N / W input groups. Multichannel switch 3 can have for each branch 2.1, 2.2 delay lines, respectively W, multiplexers 3.1.1–3.1.W, 3.2.1–3, which are controlled by means of the counterpart 8. 2.W with N / W inputs, the corresponding inputs of which are connected to the respective tap of separate groups of trunks. In an exemplary embodiment, in which one after another the following taps are combined into a group, the taps 2.1.0, 2.1.1 forming such a group, having such taps 2.1.0-2.1. (D1-1) of branch 2.1 of delay line 2, the first inputs of both multiplexers 3.1.1 and 3.1.W are connected to the corresponding branches of this group of taps, and the next group of both taps 2.1.2 and 2.1.3 is connected to the second inputs of these multiplexers, etc., taps 2.1. (M-2 ) and 2.1 (N-1), forming the last group of taps, are connected to the last inputs of both multiplexers 3.1.1 and 3.1.W.
    In a similar way, the taps of the second branch 2.2 of the delay line are connected to the inputs of multiplexers 3.2.1-3.2.W.
    Multichannel switch 3, formed by four multiplexers 3.1.1-3.2.W, can be N / W times faster than 2 delay lines, so that for each delay step, i.e. at each time element, all taps of the delay line are read.
    The outputs of the multiplexers 3.1.1- 3.2.W are connected to a common coding unit 4, formed in the example of execution by means of a fixed memory unit (ROM), in which a pair of consecutive ternary signal elements read by means of the multi-channel switch 3, i.e. . the quadrupole corresponding to such a pair of elements of the ternary signal.
    can be recoded by the following table. 1 using the binary signal elements appearing on the corresponding branches of both of the 2.1 and 2.2 delay lines.
    In tab. 1 in t columns
    and t
    25
    possible pairs of successive ternary elements are given
    10 signals, and in the columns of ch. 1.1, in.l.W, m. ; .. 1 and m.2.W correspond to them, appearing at the outputs of multiplexers 3.1.1, 3.1.W, 3.2.1 and 3.2.W bits of the signal signal and the signal of the module. In view of the vanities at the outputs of the coding block 4, the control bits P | -PJ-, corresponding to the individual quadrupoles of the signal bits of the sign and the signal of the module, are given in Table. 1 in columns P, -PS-. In this case, the control bits of the p- and rf, in addition to the group address issued by the counter 8, serve as a sample of the accumulative cells of the accumulator 5 of the signals of partial sums.
    In the accumulator 5, performed with adaptive filtering of signals, as a read and write accumulator (RAM), partial sum signals accumulate corresponding to A N / W
    30 combinations W of each other of the following signal elements of the A-significant digital signal from N / W of each other of the following groups of elements of the digital signal of the corresponding, evaluated according to the corresponding filter setting of the elements of the signal of the outlet. In the example considered here, versions with and in drive 4 are under each group address, i.e. respectively 4Q is responsible for each j-th group of taps (c),. . .N / W-1), in principle, accumulate partial amounts indicated respectively in column F of the table. 2, where the individual terms are
    45 corresponding to this index filter coefficients. It can be seen that, in principle, they accumulate partial sums corresponding to possible combinations of one after another.
    50 ternary signal elements, of the corresponding, estimated according to the filter setting, i.e. multiplied by the corresponding filter coefficients elements tk 2- signal from
    5 water, from which atem according to the pairs of P3 P4 control bits - and thus I. In accordance with the read signal elements of the retraction signal, a clock is read
    the exact amount.
    I
    In tab. 2 in column F are given for 9 possible combinations,
    4-2JH ((1) TR ° EARNED SIGNALS and for the corresponding Table 1 control bits p. ,, p resultant according to the extrusion V-r
    F (k, J) CWJ. + V
    private sums and estimated using coefficient C; element filter a; signal of the removal of a group of such elements of the signal.
    The capacity of the accumulator required for accumulating partial sums is reduced if only partial sum signals that are different from zero are accumulated, and if, with a digitally symmetric digital signal, they only remember the partial sum signals that differ only in their sign, then in each step of the delay in accordance with the actual combination of elements the digital signal is added or subtracted sequentially read signals of partial sums to form an element of the output signal, as well as again to be ominaniyu corrected partial sum signal. Thus, as can be seen from the following explanations, the scheme according to the drawing also works.
    The output of the accumulator 5 partial sums is connected to the input register 6.2 of the signal summing unit 6, the output signal of which is fed to the input of the input register 6.3, which makes it possible to successively sum the signals of the partial sums read for each delay step from the accumulator 5. And appearing To the output of the coding block 4, the control bit (p2 in Table 1) indicates the addition (at P2 (0 or subtracted (at p 1)) the partial sum in the input register 6.2, by means of the control bit (p, 0 in the tab. 1) encoding the output device 4, the input register 6.2 is locked, if the instantaneous amount of the convolution is reached must remain unchanged, so neither addition nor subtraction takes place. If during the delay element, the partial sum signals corresponding to appearing 1. .1.0-; l.1 (N-1), 2.2.0-2.:. (N-1) delay lines for digital signal elements,
    five
    0
    five
    0
    five
    0
    five
    0
    five
    those. If the corresponding signals of partial sums for the corresponding delay step are added together with each other and in accordance with N / W valid combinations of ternary signals, the corresponding processed signal is output at the output of block 6, i.e. filtered, the element of the output signal G.
    So that the input digital signal is correctly processed into a digital output signal, i.e. to a certain extent (in the time range) filtered, the partial sum signals corresponding to the desired filter characteristic should be accumulated in the accumulator of 5 partial sums. In the scheme, the partial sum signals from the adaptation process are iteratively generated by the fact that each of the successively read partial sum signals, combined with a correlation value, forms the corrected partial sum signal, like a new partial sum signal. For this, the output of accumulator 5 is connected to one input register 7.3 of an additional block 7, which is also controlled by a coding block and which has a second input register 7.2 for the signal D generated by a control variable that appears during each delay step b. The output of the additional unit 7, on which the signal Sj is formed, is connected to the recording input of the accumulator 5.
    The error signal u GK is the deviation of the output signal G from a predetermined value and can be formed in various ways, for example, by subtracting the output signal O of the same output signal, estimated using a 1-Chmitt trigger.
    The & Cc error signal can also be appropriately averaged and / or should also be effective only in its sign, which, however, should not be traced in more detail either.
    The LQk error signal in addition to the estimate using the regulating quantity g can also be estimated using the q value, i.e. to be multiplied, and depending on the control bit output by the coding block, the value of q at) is 1 or (at) value 2. As can be seen from the table. 1 q value is equal to
    the sum of the squares of the readout signal elements of the tap. By further estimating the error signal using this sum of squares of the elements of the tap signal or using
    scalar product aa; vecto / g 7 G0
    pa (..vector - string a t:) describing using its partial components .yr,
    ), . . , W-1.) C.Mb.Nvnnost of the digital signal elements appearing in the k-th time stamp in taps along the delay line 2, to itself (vector - column a t-;) - if necessary, The adaptation of partial sums, described with:
     F (, pa a „J.
    In tab. 2 is represented with a digital signal with three values (ternary signaling) and grouping, respectively, W. I, of the retraction elements, nine possible partial sums F (k, j). If a two-digit should be processed instead, i.e. having only two values 1 and -1 a digital signal (binary signal), and unlike the drawing, then in the absence of 1 code converter, it is required to provide only one branch of delay line 2, then when grouped together, respectively, elements of the tap-off signals, only four two-link are possible. - ny partial amounts of F tab. 2
    In general, the accumulation of partial sums with an A-significant, digitally symmetric digital signal requires a storage capacity of 5 equal to: 1/2-A -N / W partial sums with an even value A of the digital signal to be processed, the coefficient 1/2 occurring because With the digital signal symmetry, only half of the possible amounts of partial sums should be accumulated. With an odd value of A, the number of subjects to be accumulated in the amounts of partial sums is reduced by one, since it is not necessary to memorize, in which case capacitance 5 is required, equal to 1/2 (A - 1) N / W of partial sums.
    In tab. Figure 3 shows the number N./W of arithmetic operations required by the delay step for different group lengths, as well as the storage capacitance required for accumulating partial sums for a symmetric binary signal and for a symmetric ternary signal.
    It can be seen that when the number of required arithmetic operations is halved (in comparison with the corresponding known
    transversal filter), and the storage capacity is required when filtering a binary signal is not attempted while filtering the ternary signal it doubles.
    20
    five
    0
    five
    0
    five
    0
    five
    权利要求:
    Claims (6)
    [1]
    Invention Formula
    one . A method of processing digital signals according to the type of preferred adaptive transversal filter, which consists in incrementally delaying the time of signal elements passing through (N-1) delay time steps, accumulating signals that correspond to a group of delayed signal elements estimated taking into account mass coefficients the passage of the elements of the signals, taking into account the actual combinations of the delayed elements of the signals, the corresponding signals are sequentially read, summed with each other With the formation of elements of the output signal, characterized in that, in order to improve speed, the accumulation of sum signals is carried out by summing the partial sums of the corresponding N / W (where) the following A groups, where A is the number of element signal equations, W is the number of successive elements in the group of delayed elements of the signal, possible combinations of those following one after another in the group of delayed elements of the signal, while during each step of the time of passage of the signal elements taking into account N / W valid combinations Inations of delayed signal elements, the corresponding partial sum signals are sequentially read and summed with each other to form the elements of the output signal.
    2. The method according to claim 1, characterized in that each of the successively read partial signals
    [2]
    The sums are combined with the correlation quantity and form a corrected partial sum signal, which is accumulated as a new partial sum signal.
    3. The method according to claim 2 is different in that, during each step of the signal cell transit time, the individual partial sum signals are corrected in accordance with the output signal error occurring during the signal cell transit time step set value.
    [3]
    4. The method according to claim 3, wherein the individual signals of partial sums are corrected in accordance with the error of the output signal,
    [4]
    estimated using the installation of the largest of the inputs of the additional unit
    ins and sum of squares of the elements of the signal.
    5. The method according to paragraphs. 1-4, which is distinguished by the fact that partial sum signals, differing in their sign, accumulate once, during successive steps of the signal elements, the successively read partial sum signals are either added or subtracted in accordance with the actual element combination. or for a partially reworking signal of partial sums to be memorized.
    [5]
    6. A device for processing digital signals of a type of preferably adaptive transversal filter, comprising a delay line with (N-1) tap-off steps, the input of which is the input of the device, a summation unit and a multi-channel switch characterized by
    [6]

    + 1
    about
    -one
    + 1
    about
    -one
    + 1
    about -1
    oh oh oh oh oh i
    L l
    ABOUT
    about
    L
    ABOUT
    about
    L
    O;) I,
    L L L O O O L L L
    the fact that a coding block is entered, a partial sum accumulator, and a multichannel switch are made with W outputs, where W is the number of taps of the delay line in each of the N / W groups, the i-inputs of which are connected to the taps of the i-th group of N / W groups taps of the delay line, the outputs of the multichannel switch are connected to the inputs of the coding unit, the outputs of which are connected to the inputs of the partial sum accumulator, the output of which is connected to one of the inputs of the summation unit,
    5, the output of which is connected to its other input and is the output of the device.
    /. A device according to claim 6, characterized in that the output of the partial sum accumulator is connected to the one summation, the output of which is connected to the recording input of the partial sum accumulator, and the other input of the additional summation unit is the 5 input of the error signal, estimated using the setting value.
    8. Device popp. 6 and 8, about t - in particular, because the multi-channel switch is made in the form of W multiplexers with N / W number of inputs.
    9. The device according to paragraphs. 6-8, characterized in that the encoding unit is designed as a permanent storage device.
    10. Device on PP. 6-9, characterized in that the delay line contains two branches with (N-1)
    Q steps of taps, the inputs of which are connected to two outputs of the converter of the ternary signal into a signal of a module and a sign, respectively. Table 1
    five
    L L L L L L L
    0 d 0
    L
    L
    L l l
    L I
    0 L
    .))
    L
    L
    0 l 0
    0 L 0 L
    L 0 L 0
    0 l 0
    L
    Table
    类似技术:
    公开号 | 公开日 | 专利标题
    SU1655309A3|1991-06-07|Digital signal processing method based preferably on use of adaptive transversal filter and device therefor
    US4486900A|1984-12-04|Real time pitch detection by stream processing
    US3665171A|1972-05-23|Nonrecursive digital filter apparatus employing delayedadd configuration
    US3906400A|1975-09-16|Transfer function realization with one-bit coefficients
    US3544775A|1970-12-01|Digital processor for calculating fourier coefficients
    EP0372350B1|1995-02-15|Programmable digital filter
    US3822404A|1974-07-02|Digital filter for delta coded signals
    CN1126320C|2003-10-29|Sample rate converter
    US4228517A|1980-10-14|Recursive filter
    US4727505A|1988-02-23|Convolution arithmetic circuit for digital signal processing
    US5506798A|1996-04-09|Digital filter and oversampling analog to digital converter employing the same
    US4185325A|1980-01-22|Recursive digital filter having coefficients equal to sums of few powers of few powers of two terms
    US4866648A|1989-09-12|Digital filter
    US5586068A|1996-12-17|Adaptive electronic filter
    US3959637A|1976-05-25|Digital filter
    US4809209A|1989-02-28|Mybrid charge-transfer-device filter structure
    US4992967A|1991-02-12|Digital filter using fourier transformation
    US4701875A|1987-10-20|High speed convolution arithmetic circuit with multiple counters
    US3714402A|1973-01-30|Digital filter employing serial arithmetic
    US4027147A|1977-05-31|Binary multiplication unit with partial product and sum calculation time higher than multiplicand bit interval
    US4052605A|1977-10-04|Interpolating non-recursive digital filter
    US5928314A|1999-07-27|Digital filter having a substantially equal number of negative and positive weighting factors
    US5128886A|1992-07-07|Using long distance filters in the presence of round-off errors
    EP0156648B1|1992-09-30|Convolution arithmetic circuit for digital signal processing
    US5053984A|1991-10-01|Memory for programmable digital filter
    同族专利:
    公开号 | 公开日
    YU212084A|1987-02-28|
    HU189450B|1986-07-28|
    FI844920A0|1984-12-13|
    FI83009B|1991-01-31|
    DE3472342D1|1988-07-28|
    EP0149785B1|1988-06-22|
    NO166988C|1991-09-18|
    AT35354T|1988-07-15|
    LU85388A1|1984-09-11|
    CA1215132A|1986-12-09|
    JP2812679B2|1998-10-22|
    HUT36302A|1985-08-28|
    JPS60144014A|1985-07-30|
    UA6011A1|1994-12-29|
    AU577496B2|1988-09-22|
    FI83009C|1991-05-10|
    EP0149785A1|1985-07-31|
    FI844920L|1985-06-15|
    ZA849663B|1985-07-31|
    NO166988B|1991-06-10|
    US4701873A|1987-10-20|
    NO844870L|1985-06-17|
    DE3345284A1|1985-06-27|
    AU3663684A|1985-06-20|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US3993890A|1975-09-29|1976-11-23|The United States Of America As Represented By The Secretary Of The Air Force|Combinatorial digital filter|
    FR2346911B1|1975-12-22|1981-09-18|Trt Telecom Radio Electr|
    JPS6031127B2|1976-02-06|1985-07-20|Nippon Electric Co|
    US4369499A|1980-09-18|1983-01-18|Codex Corporation|Linear phase digital filter|
    US4374426A|1980-11-14|1983-02-15|Burlage Donald W|Digital equalizer for high speed communication channels|
    US4377793A|1981-01-13|1983-03-22|Communications Satellite Corporation|Digital adaptive finite impulse response filter with large number of coefficients|
    US4468786A|1982-09-21|1984-08-28|Harris Corporation|Nonlinear equalizer for correcting intersymbol interference in a digital data transmission system|
    IT1159389B|1983-04-19|1987-02-25|Cselt Centro Studi Lab Telecom|ADAPTIVE EQUALIZER FOR NUMERICAL SIGNALS|
    US4550415A|1983-11-16|1985-10-29|At&T Bell Laboratories|Fractionally spaced equalization using nyquist-rate coefficient updating|
    US4615026A|1984-01-20|1986-09-30|Rca Corporation|Digital FIR filters with enhanced tap weight resolution|DE3414129A1|1984-04-14|1985-10-24|Standard Elektrik Lorenz Ag, 7000 Stuttgart|Adaptive equaliser for digital data transmission systems with a transmission speed above the Nyquist frequency|
    US4931973A|1986-07-30|1990-06-05|Asghar Safdar M|Method of generating updated transversal filter coefficients|
    US4809208A|1987-04-03|1989-02-28|Tektronix, Inc.|Programmable multistage digital filter|
    DE3879838D1|1987-09-30|1993-05-06|Siemens Ag|METHOD AND CIRCUIT FOR GENERATING FILTER SIGNALS.|
    US5293611A|1988-09-20|1994-03-08|Hitachi, Ltd.|Digital signal processor utilizing a multiply-and-add function for digital filter realization|
    DE3841268A1|1988-12-08|1990-06-13|Thomson Brandt Gmbh|DIGITAL FILTER|
    JPH0828649B2|1989-02-16|1996-03-21|日本電気株式会社|Digital filter|
    JP3011948B2|1989-07-31|2000-02-21|パイオニア株式会社|Digital equalizer|
    EP0413073A1|1989-08-16|1991-02-20|International Business Machines Corporation|Adaptive loop gain phase filter|
    US5584034A|1990-06-29|1996-12-10|Casio Computer Co., Ltd.|Apparatus for executing respective portions of a process by main and sub CPUS|
    US5200564A|1990-06-29|1993-04-06|Casio Computer Co., Ltd.|Digital information processing apparatus with multiple CPUs|
    JPH04270510A|1990-12-28|1992-09-25|Advantest Corp|Digital filter and transmitter|
    EP0545581B1|1991-12-06|1999-04-21|National Semiconductor Corporation|Integrated data processing system including CPU core and parallel, independently operating DSP module|
    DE10302113B4|2003-01-21|2017-12-28|Lantiq Deutschland Gmbh|Method and device for reducing the crest factor of a signal|
    DE10302161A1|2003-01-21|2004-08-05|Infineon Technologies Ag|Crest factor method for altering the crest factor in a time-discrete signal formed by a signal vector's time-consecutive signal value calculates a correcting vector to add to the signal vector|
    US7672393B2|2006-08-02|2010-03-02|Richtek Technology Corporation|Single-wire asynchronous serial interface|
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    DE19833345284|DE3345284A1|1983-12-14|1983-12-14|METHOD AND CIRCUIT ARRANGEMENT FOR DIGITAL SIGNAL PROCESSING IN THE TYPE OF A PREFERABLY ADAPTIVE TRANSVERSAL FILTER|
    [返回顶部]